1. Field of the Invention
The invention relates in general to an IC “layout vs. schematic” (LVS) physical verification method for detecting connectivity and uniformity violations in an on-chip drawn inductor, for verifying its shape, and for extracting the inductor device and its parameters.
2. Description of Related Art
An integrated circuit (IC) designer may initially generate an IC design in the form of a schematic netlist referencing instances of the IC circuit devices (“cells”) to be included in the IC, referencing the nets to convey signals within the IC, and indicating the cell instance terminals to be connected to each net. Thereafter the designer may use a computer-aided design tool to generate an IC layout indicating how and where each circuit device is to be formed within the IC and describing the actual route conductors within the IC are to follow to interconnect device terminals. A typical IC consists of several layers of semiconductor, insulator and conductive material and an IC layout includes binary data associated with each layer of the IC mapping the geometric material or doping patterns needed to implement the various cells.
After generating an IC layout, a designer will often employ a “layout vs. schematic” (LVS) physical verification tool to verify that device components such as gates, transistors, resistors and capacitors and their interconnections are consistent with the schematic or netlist description of the IC. An LVS tool processes the IC layout to identify IC circuit devices and interconnects based on their representative geometric patterns and to create another netlist describing the IC represented by the layout. Following this “extraction” process, the LVS tool reviews the extracted netlist to identify errors in the layout including shorts and opens and malformed devices. The LVS tool also compares the extracted netlist to the original netlist to determine whether there are any differences with respect to relative to devices, interconnection and circuit parameters.
One of the components that an IC may include is a drawn inductor, a passive circuit component used for example, in cell phones, global positioning system (GPS) receivers and other modern portable communication systems. Recently, design engineers have begun to incorporate drawn inductors into analog and Radio Frequency (RF) ICs. An on-chip drawn inductor typically includes one or more conductors formed in the shape of a spiral having an inductance that is a predictable function of its shape. The two most common types of drawn inductors are the 3-terminal center tap inductor and the 2-terminal spiral inductor. The center tap inductor include terminals on opposite ends of its spiral and a center tap terminal connected to the middle of the spiral. A spiral inductor includes a terminal on an outer end of is spiral and a center tap terminal connected to inside end of its spiral. To generate high inductance an inductor may include multiple spiral or spoke shapes, each residing on a separate layer of the IC.
IC fabricators typically impose several design rules/restrictions on the spiral of the drawn inductor. For example, an IC fabricator may require the spiral to have a uniform wire width and uniform spacing between turns of the wire, to have a uniform inner diameter and uniform “bend angles” between successive straight sections of wire forming the spiral. For example, a spiral may include only 45 degree bend angles or only 90 degree bends but may not include both 45 degree and 90 degree bend angles.
Since a drawn inductor is defective if it breaks any of the above rules, it is helpful before submitting an IC layout design for fabrication to perform a “uniformity check” of each drawn inductor within the layout to determine whether it satisfies the above rules. It is also helpful to perform a “connectivity check” on each drawn inductor to determine whether it its spiral and its center tap or spoke terminal are correctly interconnected and to determine whether multiple layers of conductors and vias forming an inductor terminal are properly interconnected. A designer will also want to verify the inductance of each drawn inductor by first measuring the geometric parameters influencing the inductor's inductance such as, for example, its spiral length, spacing between spiral turns, spiral inner diameter, total number of turns, and the number of sides per turn. The designer can then calculate the inductor's inductance based on such parameters by using well-known inductance formula, such as, for example, the Current Sheet Approximation Formula described in “Simple Accurate Expressions for Planar Spiral Inductances” by S. Mohan, et al., IEEE J. Solid-State Circuits, vol. 34, pp. 1419–1424, October 1999.
Currently, a design engineer using an LVS tool for physical verification of on-chip drawn chip inductors must generate a large number of device extraction commands to extract the components of the drawn inductors in the layout and then use a series of device parameter extraction rules to measure the inductor parameters and calculate the inductance. The designer usually has difficulty extracting a drawn inductor's geometric parameters due to the complex nature of its spiral shape, and when multiple layers form each terminal of the device, the designer finds it hard to check the proper connectivity between the multiple layers.
Thus employing prior art LVS tools a user must write hundreds of commands to check drawn inductors for shape and connectivity violations and to perform drawn inductor extraction. What is needed is a method for use by an LVS tool that can respond to a single command by quickly and efficiently recognizing drawn inductors in a layout, detecting shape and connectivity violations in those drawn inductors and extracting inductor device parameters.